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SyncMOS Technologies Inc.
September 2002
SM89516A
8 - Bit Micro-controller
with 64KB flash & 1KB RAM embedded
Product List
SM89516AL25, 25MHz 64KB internal flash MCU SM89516AC25, 25MHz 64KB internal flash MCU SM89516AC40, 40MHz 64KB internal flash MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version 4.5V ~ 5.5V For C Version General 8052 family compatible 12 clocks per machine cycle 64K byte on chip program flash 1024 byte on-chip data RAM Three 16 bit Timers/Counters One Watch Dog Timer Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package Full duplex serial channel Bit operation instruction Industrial Level 8-bit Unsigned Division 8-bit Unsigned Multiply BCD arithmetic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and Power down mode Code protection function Low EMI (inhibit ALE) Bank mapping direct addressing mode for access on-chip RAM 5 channel SPWM function with P1.3 ~ P1.7
Description
The SM89516A series product is an 8 - bit single chip micro controller with 64KB on-chip flash and 1K byte RAM embedded. It is a derivative of the 8052 micro controller family. It has 5-channel SPWM build-in. User can access on-chip expanded RAM with easier and faster way by its `bank mapping direct addressing mode' scheme. With its hardware features and powerful instruction set, it's straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 I/ O pins for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 64K byte flash memory for program data. To program the on-chip flash memory, a commercial writer is available to do it in parallel programming method.
Ordering Information
yywwv SM89516Aihhk yy: year, ww:week v: version identifier {, A, B,...} i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table} v: version identifier
Postfix P J Q
Package 40L PDIP 44L PLCC 44L QFP
Pin/Pad Configuration page 2 page 2 page 2
Dimension page 21 page 22 page 23
Taiwan 4F, No. 1 Creation Road 1, Science-based Industrial Park, Hsinchu, Taiwan 30077 TEL: 886-3-578-3344 #2667 886-3-579-2987 FAX: 886-3-5792960 886-3-5780493
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
Pin Configurations
P1.4/SPWM1
P1.3/SPWM0 P1.2
P0.4/AD4
P0.5/AD5
P0.6/AD6
P1.1/T2EX P1.0/T2 P4.2 VDD P0.0/AD0 P0.1/AD1
P0.7/AD7 #EA
P2.7/A15
P0.2/AD2
P0.3/AD3
6
5
4
32
1 44 43 42 41 40
SPWM2/P1.5 SPWM3/P1.6 SPWM4/P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5
7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13
AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VDD P4.2 T2/P1.0 T2EX/P1.1 P1.2 SPWM0/P1.3 SPWM1/P1.4
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
ALE
P2.6/A14 P2.5/A13
P4.1
#PSEN
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0A8 P4.0 VSS XTAL1 XTAL2 P3.7/#RD P3.6/#WR
SM89516A ihhJ 44L PLCC
SM89516A ihhQ 44L QFP
(Top View)
14 (Top View) 15 16 17 18 19 20 21 22 23 24 25 26 27 28
#WR/P3.6
#RD/P3.7 XTAL2 XTAL1 VSS
P4.0
A10/P2.2
A12/P2.4
A8/P2.0
A9/P2.1
A11/P2.3
SPWM2/P1.5
SPWM3/P1.6 SPWM4/P1.7 RES
P4.3
T0/P3.4
RXD/P3.0
TXD/P3.1
T2/P1.0 T2EX/P1.1 P1.2 SPWM0/P1.3 SPWM1/P1.4 SPWM2/P1.5 SPWM3/P1.6 SPWM4/P1.7 RES RXD/P3.0 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
7 8
9 10 11
12
13 14 15 16 17 18 19 20
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/25
#INT0/P3.2
#INT1/P3.3
Ver 1.2
T1/P3.5
SM89516AihhP 40L PDIP
(Top View)
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Block Diagram
Timer 2 Timer 1 Timer 0 Stack Pointer Decoder & Register 1024 bytes RAM
SM89516A
WDT
RES Reset Circuit to pertinent blocks Acc to whole chip Buffer2 Buffer1
Buffer
DPTR
Vdd Vss
Power Circuit
PC Incrementer
Interrupt Circuit
to pertinent blocks
ALU
Program Counter
XTAL2 XTAL1 #EA ALE #PSEN Timing Generator to whole system
PSW
Register
FFFFH Instruction Register
64K bytes Flash Memory
Port 0 Latch 5
Port 1 Latch
Port 2 Latch
Port 3 Latch
Port 4 Latch
SPWM
0000H
Port 0 Driver & Mux 8 Port 1 Driver & Mux 8 Port 2 Driver & Mux 8 Port 3 Driver & Mux 8 Port 4 Driver & Mux 4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
Pin Descriptions
40L 44L 44L PDIP QFP PLCC Pin# Pin# Pin#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 17 28 39 6 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 23 34 1 12
Symbol
P1.0/T2 P1.1/T2EX P1.2 P1.3/SPWM0 P1.4/SPWM1 P1.5/SPWM2 P1.6/SPWM3 P1.7/SPWM4 RES P3.0/RXD P3.1/TXD P3.2/#INT0 P3.3/#INT1 P3.4/T0 P3.5/T1 P3.6/#WR P3.7/#RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 #PSEN ALE #EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.0 P4.1 P4.2 P4.3
Active I/O
i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o
Names
bit 0 of port 1 & timer 2 clock out bit 1 of port 1 & timer 2 control bit 2 of port 1 bit 3 of port 1 & SPWM channel 0 bit 4 of port 1 & SPWM channel 1 bit 5 of port 1 & SPWM channel 2 bit 6 of port 1 & SPWM channel 3 bit 7 of port 1 & SPWM channel 4, Reset bit 0 of port 3 & Receive data bit 1 of port 3 & Transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & Timer 0 & bit 5 of port 3 & Timer 1 bit 6 of port 3 & ext. memory write bit 7 of port 3 & ext. mem. read Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of ext. memory address bit 1 of port 2 & bit 9 of ext. memory address bit 2 of port 2 & bit 10 of ext. memory address bit 3 of port 2 & bit 11 of ext. memory address bit 4 of port 2 & bit 12 of ext. memory address bit 5 of port 2 & bit 13 of ext. memory address bit 6 of port 2 & bit 14 of ext. memory address bit 7 of port 2 & bit 15 of ext. memory address program storage enable address latch enable external access bit 7 of port 0 & data/address bit 7 of ext. memory bit 6 of port 0 & data/address bit 6 of ext. memory bit 5 of port 0 & data/address bit 5 of ext. memory bit 4 of port 0 & data/address bit 4 of ext. memory bit 3 of port 0 & data/address bit 3 of ext. memory bit 2 of port 0 & data/address bit 2 of ext. memory bit 1 of port 0 & data/address bit 1 of ext. memory bit 0 of port 0 & data/address bit 0 of ext. memory Drive Voltage, +5 Vcc bit 0 of Port 4 bit 1 of Port 4 bit 2 of Port 4 bit 3 of Port 4
H
L/ L/ -
L
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Special Function Register (SFR)
SM89516A
The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general 8052, as well as SM89516A Extension SFRs.
Special Function Register (SFR) Memory Map
$F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 ACC P4 PSW T2CON IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 (Reserved) TH1 RCON DBANK PCON SBUF SPWMC P1CON SPWMD4 SPWMD0 SPWMD1 SPWMD2 SPWMD3 WDTC WDTKEY T2MOD RCAP2L RCAP2H TL2 TH2 SCONF B $FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM89516A
Addr 85H 86H 97H 9BH 9FH A3H A4H A5H A6H A7H ACH BFH C8H C9H D8H SFR RCON DBANK WDTKEY P1CON WDTC SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3 SPWMD4 SCONF T2CON T2MOD P4 Reset ******00 0***0001 00H 00000*** 0*0**000 ******00 00H 00H 00H 00H 00H 0*****00 00H ******00 ****1111 P4.3 P4.2 SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10 SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20 SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30 SPWMD44 SPWMD43 SPWMD42 SPWMD41 SPWMD40 WDR TF2 EXF2 RCLK TCLK EXEN2 TR2 BRM02 BRM12 BRM22 BRM32 BRM42 BSE SPWME4 WDTE SPWME3 SPWME2 CLEAR SPWME1 BS3 SPWME0 PS2 PS1 SPFS1 BRM01 BRM11 BRM21 BRM31 BRM41 OME C/T2 T2OE P4.1 PS0 SPFS0 BRM00 BRM10 BRM20 BRM30 BRM40 ALEI CP/RL2 DCEN P4.0 BS2 7 6 5 4 3 2 1 RAMS1 BS1 0 RAMS0 BS0
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
Extension Function Description
1. Memory Structure
The SM89516A is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general 8052 structure.
1.1 Program Memory
The SM89516A has 64K byte on-chip flash memory which used as general program memory. The address range for the 64K byte is $0000 to $FFFF. FFFF
64K Program memory space
0000 Note: The single flash block address structure for doing as well as program ROM flash.
1.2 Data Memory
The SM89516A has 1K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 768 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by `Bank mapping direct addressing mode' as described in next page.
02FF
Expanded 768 bytes RAM (Accessed by direct external addressing mode, by instruction MOVX, or by Bank mapping direct addressing mode) FF
FF Higher 128 bytes (Access by 7F 80 indirect addressing mode only)
SFR (Accessed by direct addressing mode only)
80
(OME = 1)
Lower 128 bytes (Accessed by
direct & indirect addressing mode) 00
On-chip expanded RAM address structure.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
0000
6/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052. The address $00 to $7F can be accessed by direct and indirect addressing modes. Address $00 to $1F is register area. Address $20 to $2F is memory bit area. Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode. Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 768bytes ($0000 to $02FF, Bank 4 ~ Bank 15)
From external address $0000 to $02FF is the on-chip expanded RAM area, total 768 bytes. This area can be accessed by external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described below:
1.3 Bank mapping direct addressing mode:
We provide RAM bank address `40H~7FH' as mapping window which allow user access all the 1KB on-chip RAM through this RAM bank address. That means using direct addressing mode can access all the 1KB on-chip RAM. Please see next page for the mapping mode table.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
7/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
BS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
040h~07fh mapping address 000h~03fh 040h~07fh 080h~0bfh 0c0h~0ffh 0000h~003fh 0040h~007fh 0080h~00bfh 00c0h~00ffh 0100h~013fh 0140h~017fh 0180h~01bfh 01c0h~01ffh 0200h~023fh 0240h~027fh 0280h~02bfh 02c0h~02ffh
Note lower 128 byte RAM lower 128 byte RAM higher 128 byte RAM higher 128 byte RAM on-chip expanded 768 byte RAM " " " " " " " " " " "
With this bank mapping scheme, user can access entire 1K byte on-chip RAM with direct addressing method. That means using the window area ($040~$07F), user can access any bank (64 byte) data of 1K byte on-chip RAM space which is selected by BS[3:0] of data bank control register (DBANK, $86). For example, user write #30h to $101 address : MOV DBANK, #88H ; set bank mapping $040~$07f to $0100~$013f MOV A, # 30H ; store #30H to A MOV 41H, A ; write #30H to $0101 address
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Data Bank Control Register (DBANK, $86)
bit-7 BSE Read / Write: Reset value: R/W 0 Unused * Unused * Unused * BS3 R/W 0 BS2 R/W 0 BS1 R/W 0
SM89516A
bit-0 BS0 R/W 1
Data bank select enable bit BSE = 1 enables the data bank select function Data bank select enable bit BSE = 0 disables the data bank select function BS[3:0] setting will map $040~$07F RAM space to entire 1K byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * Unused * RAMS1 R/W 0 bit-0 RAMS0 R/W 0
SM89516A has 768 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 1 and bit 0 (RAMS1, RAMS0) of RCON. The default setting of RAMS1, RAMS0 bits is 00 (page0). RAMS1 0 0 1 RAMS0 0 1 0 MOVX @Ri i=0,1 mapping to expended RAM address $0000 ~ $00FF $0100 ~ $01FF $0200 ~ $02FF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow. WDR will be set to 1, The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
OME : 768 bytes on-chip RAM enable bit. The bit 0 (OME) of SCONF can enable or disable the on-chip expanded 768 byte RAM. The default setting of OME bit is 0 (disable). ALEI : ALE output inhibit bit, to reduce EMI. Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin.
1.4 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a `1' which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. Writing `1' to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input. The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output data input data
pin
port 0 standard 8051
output data input data
port 1, 2 and 3 standard 8051
pin
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * P4.3 R/W 1 P4.2 R/W 1 P4.1 R/W 1 bit-0 P4.0 R/W 1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively. The port 4 output buffers can sink 20mA and can drive LED display directly.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/25
Ver 1.2
SM 89516A 09/02
SyncMOS Technologies Inc.
September 2002 3.Watch Dog Timer
SM89516A
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway. There is a 250KHz RC oscillator embedded in chip. Set WDTE = "1" will enable the RC oscillator and the frequency is independent to the system frequency. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM59264 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
3.1 Watch Dog Timer Registers: Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7 WDTE Read / Write: Reset value: R/W 0 Reserve * CLEAR R/W 0 Unused * Unused * PS2 R/W 0 PS1 R/W 0 bit-0 PS0 R/W 0
WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits PS [2:0] 000 001 010 011 100 101 110 111
Specifications subject to change without notice,contact your sales representatives for the most recent information.
Overflow Period (ms) 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.144
11/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Watch Dog Key Register - (WDTKEY, $97H)
bit-7 WDT KEY7 Read / Write: Reset value: W 0 WDT KEY6 W 0 WDT KEY5 W 0 WDT KEY4 W 0 WDT KEY3 W 0 WDT KEY2 W 0 WDT KEY1 W 0
SM89516A
bit-0 WDT KEY0 W 0
By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to enable the WDTC write attribute, That is MOV WDTKEY, # 1EH MOV WDTKEY, # E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # E1H MOV WDTKEY, # 1EH
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened
4. Reduce EMI Function
The SM89516A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
5. Specific Pulse Width Modulation (SPWM)
The Specific Pulse Width Modulation (SPWM) module contain 1 kind of PWM sub module: SPWM (Specific PWM). SPWM has five 8-bit channels.
5.1 SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock speed. The SPFS[1:0] settings of SPWMC ($A3) register are dividend of Fosc to be SPWM clock, Fosc/2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/2^(SPFS[1:0]+1)]/32.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
5.2 SPWM Registers - P1CON, SPWMC, SPWMD[4:0] SPWM Registers - Port1 Configuration Register (P1CON, $9B)
bit-0 SPWME4 Read / Write: Reset value: R/W 0 SPWME3 R/W 0 SPWME2 R/W 0 SPWME1 R/W 0 SPWME0 R/W 0 Unused * Unused * Unused *
SPWME[4:0] : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to zero, the corresponding SPWM pin is active as I/O pin. Five bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, $A3)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * Unused * SPFS1 R/W 0 bit-0 SPFS0 R/W 0
SPFS[1:0]: These two bits is 2's power parameter to form a frequency divider for input clock. SPFS1 0 0 1 1 SPFS0 0 1 0 1 Divider 2 4 8 16 SPWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz SPWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz
SPWM Registers - SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4)
bit-7 SPWMD [4:0]4 Read / Write: Reset value: R/W 0 SPWMD [4:0]3 R/W 0 SPWMD [4:0]2 R/W 0 SPWMD [4:0]1 R/W 0 SPWMD [4:0]0 R/W 0 BRM [2:0]2 R/W 0 BRM [2:0]1 R/W 0 bit-0 BRM [2:0]0 R/W 0
SPWMD[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform. BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/25
Ver 1.2
SM 89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
N = BRM[2:0] 000 001 010 011 100 101 110 111 Example of SPWM timing diagram: MOV SPWMC , #03H MOV SPWMD0 , #83H MOV P1CON , #08H
1st cycle frame
32T
Number of SPWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7
; Set output frequency (Divider = 16) ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3 ; Enable P1.3 as SPWM output pin
4th cycle frame 5th cycle frame
32T 32T
2nd cycle frame 3rd cycle frame
32T 32T
6th cycle frame 7th cycle frame
32T 32T
8th cycle frame
32T
16T
16T
16T
16T
16T
16T
16T
16T
1T 1T (narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
1T
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1) The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32 If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Operating Conditions
Symbol TA TS VCC5 VCC3 Fosc 16 Fosc 25 Fosc 40 Description Operating temperature Storage temperature Supply voltage Supply voltage Oscillator Frequency Oscillator Frequency Oscillator Frequency Min. -40 -55 4.5 3 3.0 3.0 3.0 Typ. 25 25 5.0 3.3 16 25 40 Max. 85 155 5.5 3.6 16 25 40 Unit.
oC oC
SM89516A
Remarks Ambient temperature under bias
V V
For C Version For L Version
MHz For 5V, 3.3V application MHz For 5V, 3.3V application MHz For 5V application
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 3.0V to 5.5V) Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current
Valid
port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0 port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit V V V V V V V V V V uA uA uA Kohm pF mA mA mA mA mA mA uA
Test Conditions
2.4 90%Vcc 2.4 90%Vcc -75 -650 + 10 300 10 15 10 20 10 7 6.5 50
IOL=3.2mA IOL=1.6mA IOH=-800uA (only for VCC =5V) IOH=-80uA IOH=-60uA (only for VCC =5 V) IOH=-10uA Vin=0.45V Vin=2.0V 0.45V50
Note1: Under steady state (non-transient) conditions, IOL must be externally Limited as follows: Maximum IOL per port pin : 10mA Maximum IOL per 8-bit port : port 0 :26mA port 1,2,3 :15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Note2 : Minimum VCC for Power-down is 2V.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 AC Characteristics
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT fosc=16MHz Min. Typ. Max 115 43 53 240 53 173 177 0 87 292 10 365 365 302 0 145 590 542 178 197 230 403 38 73 53 Variable fosc Unit Min. Typ. Max 2xT - 10 nS T - 20 nS T - 10 nS 4xT - 10 nS T - 10 nS 3xT - 15 nS 3xT - 10 nS 0 nS T + 25 nS 5xT - 20 nS 10 nS 6xT - 10 nS 6xT - 10 nS 5xT - 10 nS 0 nS 2xT + 20 nS 8xT - 10 nS 9xT - 20 nS 3xT - 10 3xT + 10 nS 4xT - 20 nS 7xT - 35 nS T - 25 nS T + 10 nS 5 nS 72 T -10 T + 10 nS nS nS nS nS 1/fosc nS Vcc
SM89516A
Remarks
63
ICC Active mode test circuit Vcc VCC RST SM89516A (NC) Clock Signal XTAL2 XTAL1 VSS PO EA 8 ICC
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Application Reference Valid for SM89516A
X'tal C1 C2 R X'tal C1 C2 R 3MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 9MHz 30 pF 30 pF open 33MHz 5 pF 5 pF 6.8K 12MHz 30 pF 30 pF open 40MHz 2 pF 2 pF 4.7K
XI X'tal
SM89516A
SM89516A
R X2 C1 C2
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
Data Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
#PSEN
#RD
PORT2
ADDRESS A15 - A8
PORT0
INST in Float
A7 - A0
Float
DATA in
Float ADDRESS or Float
Specifications subject to change without notice,contact your sales representatives for the most recent information.
17/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Program Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2
SM89516A
OSC ALE
#PSEN #RD,#WR
PORT2
ADDRESS A15 - A8
ADDRESS A15 - A8
PORT0
Float
A7 - A0
Float
INST in
Float
A7 - A0
Float
INST in
Float
Data Memory Write Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
#PSEN
#WR
PORT2
ADDRESS A15 - A8
PORT0
INST
Float
A7 - A0
DATA OUT
ADDRESS or Float
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1 inputs P0,P1
sampled
sampled
inputs P2,P3 Output by Mov Px,Src RxD at Serial Port Shift Clock (Mode 0)
current data next data
sampled
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V TCHCL TCLCX TCLCH TCHCX
Tm.I
#PSEN ALE PORT 0
External Program Memory Read Cycle
TPLPH
TLHLL TAVLL A0 - A7
TLLPL TLLAX TPLAZ TPLIV
TPXIZ TPXIX Instruction. IN A0 - A7
TAVIV
PORT 2
A8 - A15
A8 - A15
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Tm.II External Data Memory Read Cycle
SM89516A
#PSEN
TYHLH
ALE
TLLDV TLLYL TRLRH
#RD
TAVLL
TLLAX TRLAZ A0 - A7 from Ri or DPL TAVYL TAVDV
TRLDV
TRHDZ TRHDX DATA IN A0 - A7 from PCL INSTRL IN
PORT 0
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Tm.III External Data Memory Write Cycle
#PSEN
TLHLL
TYHLH
ALE
TLLYL TWLWH
#WR
TAVLL TLLAX
TQVWX
TQVWH
TWHQX
PORT 0
A0-A7 from Ri or DPL
DATA OUT
A0-A7 From PCL
INSTRL IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
40L 600mil PDIP Information
E S D E1
A1
A2 A
C
L e1 B1 B
eA a
Note: 1. Dimension D Max & include mold flash or tie bar burrs. 2. Dimension E1 does not include inter lead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dam bar protrusion/ infusion. 5. Controlling dimension is inch. 6. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 B B1 C D E E1 e1 L a eA S
Dimension in inch minimal/maximal - / 0.210 0.010 / 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0 / 15 0.630 / 0.670 - / 0.090
Dimension in mm minimal/maximal - / 5.33 0.25 / 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 0 / 15 16.00 / 17.02 - / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 44L Plastic Chip Carrier (PLCC)
6 7 L
SM89516A
E
HE y
GE
D HD A2 A A1
C
b1 e GD
b
Note: 1. Dimension D & E does not include inter lead flash. 2. Dimension b1 does not include dam bar protrusion/ intrusion. 3. Controlling dimension: Inch 4. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 b1 b C D E e GD GE HD HE L
y
Dimension in inch minimal/maximal - / 0.185 0.020 / 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 BSC 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 /
Dimension in mm minimal/maximal - / 4.70 0.51 / 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27 BSC 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 /
Specifications subject to change without notice,contact your sales representatives for the most recent information.
22/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
44L Plastic Quad Flat Package
C L S e L1 2 R1 D2 D1 D b A2 3 R2 A1 Gage Plane 0.25 mm
E2 E1 E e1 A
seating plane e
C
Note: Dimension D1 and E1 do not include mold protrusion. Allowance protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined datum plane. Dimension b does not include dam bar protrusion. Allowance dam bar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dam bar cannot be located on the lower radius or the lead foot.
Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C
Dimension in Inch minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005 / 0.005 / 0.012 0.008 / 0 / 7 0 / 10 REF 7 REF 0.004
Dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73 / 1.03 1.60 0.13 / 0.13 / 0.30 0.20 / as left as left as left as left 0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
23/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002
SM89516A
eMCU writer list
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Caprilion P.O. Box 461 KaoHsiung, Taiwan, ROC Web site: http://www.market.net.tw/ ~ cap/ Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw Xeltek Electronic Co., Ltd 338 Hongwu Road, Nanjing, China 210002 Web site: http://www.xeltek-cn.com Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number LabTool - 48 (1 * 1) LabTool - 848 (1*8)
Tel:07-3865061 Fax:07-3865421 E-mail: cap@market.net.tw
UNIV2000
Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
All - 11 (1*1) Gang - 08 (1*8)
Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw
ChipStation (1*1) SU - 2000 (1*8)
Tel:+86-25-4408399, 4543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com
Superpro/2000 (1*1) Superpro/680 (1*1) Superpro/280 (1*1) Superpro/L+(1*1)
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/25
Ver 1.2
SM89516A 09/02
SyncMOS Technologies Inc.
September 2002 Feedback / Inquiry: To Attn Fax Tel :SyncMOS Technologies, Inc. :MKT / Customer Service Dept. :886-3-579-2960 :886-3-578-0493 :886-3-579-2987 :886-3-578-3344 # 2667 From :
SM89516A
Company : Dept, Section : Position Title : Inquiry Date : Ref No :
Description:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/25
Ver 1.2
SM89516A 09/02

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